Technical Field
The present invention relates to semiconductor devices and the formation thereof and, more particularly, to reducing variation between devices by using sidewall image transfer to form gate structures.
Description of the Related Art
Conventional semiconductor fabrication uses lithography techniques to form structures. The lithography technique used, including for example the lasers and chemicals used in a given photolithography process, dictates limits on the size of features that can be created. In particular, any lithography process will have a minimum feature size that represents the smallest structure that the process can create.
One result of the physical limits of a lithographic process is line edge roughness. Line edge roughness characterizes variations in a structure below the resolution of the fabrication process. This roughness is unpredictable and is a cause of variation in the operational properties from one device to the next.
While line edge roughness contributes little to devices that have relatively large structures (e.g., a gate length of about 200 nm), fully depleted channel structures enable gate length scaling to much smaller lengths (e.g., a gate length of about 30 nm or below). At such lengths, line edge roughness can contribute significantly to device variation.